1. Field of the Invention
The present invention relates to the field of graphics. More particularly, the present invention relates to a system and method for providing a scalable, three-dimensional graphics subsystem.
2. Description of Related Art
For many years, three-dimensional (3D) graphics subsystems have been scaled in performance. Normally, this scalable performance has been accomplished by adding more memory and graphics hardware to create multiple pipelines as shown in FIG. 1. Each pipeline of the graphics subsystem renders a predetermined portion of entire image.
Referring to FIG. 1, the conventional graphics subsystem 100 receives information associated with an image targeted for display ("targeted image"). Such image information includes vertex coordinates, color, and texture coordinates of one or more triangles forming the targeted image. The image information is input into each of its rendering pipelines 110.sub.1 -110.sub.n ("n" is a positive whole number) to produce display information for each pixel of the targeted image. Each rendering pipeline 110.sub.1 -110.sub.n includes a raster subsystem 120.sub.1 -120.sub.n, a texture subsystem 130.sub.1 -130.sub.n coupled to dedicated texture memory 135.sub.1 -135.sub.n, and a pixel engine 140.sub.1 -140.sub.n coupled to a selected portion 145.sub.1 -145.sub.n of a frame buffer. The display information generated by each rendering pipeline 110.sub.1 -110.sub.n is appropriately routed to a display monitor through a multiple input multiplexer 150 controlled by a display engine. For clarity sake, the operations of a single rendering pipeline (e.g., rendering pipeline 110.sub.1) is discussed therein.
For rendering pipeline 110.sub.1, raster subsystem 120.sub.1 receives the image information and usually generates XYZ coordinates, texture coordinates and character values (color, translucency and depth) for each pixel of the image. Of course, it is contemplated that these calculations may be successively performed on portions of the targeted image (e.g., one-pixel scan line at a time) rather than the entire targeted image. This architecture has been used by Silicon Graphics, Inc. of Mountain View, Calif.
The texture subsystem 130.sub.1 receives the texture coordinates and utilizes these texture coordinates to obtain assigned texture values. The texture values are stored in dedicated texture memory 135.sub.1. Similar for all texture memories 135.sub.1 -135.sub.n, texture memory 135.sub.1 must be sized to accommodate all textures used to create the display image.
A pixel engine 140.sub.1 receives the pixel coordinates and character values from raster subsystem 120.sub.1 and texture values from texture memory 135.sub.1. Based on this information, pixel engine 140.sub.1 performs pixel level calculations in order to produce the display information. The pixel level calculations include, but are not limited or restricted to depth buffering, shadowing (referred to as "alpha blending") and fragment generation for partially covered pixels. This display information is stored in a first portion 145.sub.1 of a frame buffer reserved for rendering pipeline 110.sub.1. Under control of a display engine, the display information is transferred to digital-to-analog (D/A) conversion which are converted into a series of signals. These signals allow the display monitor produce the targeted image.
However, this technique possess a number of disadvantages. For example, in order to provide scalability, multiple texture memories 135.sub.1 -135.sub.n (e.g., dynamic random access memory "DRAM") are required. In the situation where small pixel regions (e.g., 32.times.32 pixel regions referred to as "chunks") are processed at a time, these texture memories 135.sub.1 -135.sub.n constitute an inefficient use of memory. The reason is that each texture memory 135.sub.1, . . . , 135.sub.n must be sufficiently sized to store all textures of the entire targeted image. Thus, each texture is stored "n" times which substantially increases the costs associated with scaling graphics subsystem 100.
Hence, it would be advantageous to provide a graphics subsystem that offers scalable performance with efficient use of memory.